Job DescriptionJob Function
Work on functional verification of analog and mixed-signal IPs, including SERDES, sensors, and beyond. The candidate will collaborate with IP design teams and other verification teams, utilizing and enhancing both established and emerging digital verification methodologies and processes. Responsibilities span the full verification lifecycle—from understanding specifications and developing test plans, to achieving coverage closure and supporting post-silicon debug—to ensure high-quality and efficient pre-silicon verification, ultimately delivering robust silicon products.
Skills/Experience
•Quick learner with strong critical thinking and creative problem-solving skills.
• Solid knowledge in ASIC verification flow, digital design, and UVM-based design verification methodologies.
• Proficient on using design and verification languages: UVM, Verilog, System Verilog, and System Verilog Assertions (SVA).
• Proficient on Design Verification...