Qualifications

: - Bachelor's Degree Engineering in Electrical/Electronic, Physics, Computer or related fields

- Must have good verbal and written communication skills in English. Japanese is a plus Requirements : - Thorough understanding of integrated analog circuit design.

- Thorough understanding of chip layout in cell and block level creation, edit and full verification.

- Experience with layout techniques for matching, ESD, latch-up prevention and parasitic reduction and work with an awareness and understanding of the process from physical point of view.

- Experience in analog IC/ mixed signals IC layout designs and verification. Able to perform with ideas on chip size reduction.

- Highly self-motivated and adaptable.

- Having the basic knowledge of CMOS related devices including high voltage and the skill of deciphering Design Manual.

- Layout & EDA tool skill: Expertise with Cadence and Synopsys<...